1. Field of the Invention
The present invention generally relates to AD converters for converting analog signals into digital signals, and particularly relates to a successive-approximation-type AD converter which successively compares input potentials with a reference potential.
2. Description of the Related Art
Successive-approximation-type AD converters can be implemented based on relatively simple circuit construction, and are highly suitable for CMOS processes that provide for cost-effective manufacturing. Also, comparatively high-speed conversion can be achieved. Examples of the construction of such successive-approximation-type AD converters are disclosed in Patent Document 1 and Patent Document 2 ([Patent Document 1] Japanese Patent Application Publication No. 2000-40964, and [Patent Document 2] Japanese Patent Application Publication No. 4-220016).
FIG. 1 is a circuit diagram showing the construction of a 4-bit AD converter as an example of a related-art successive-approximation-type AD converter that employs a capacitor DAC (digital-to-analog converter). The successive-approximation-type AD converter shown in FIG. 1 is shown in Patent Document 2. It should be noted that a successive-approximation-type AD converter typically has 8-bit to 10-bit precision, but a 4-bit AD converter is taken as an example for the sake of simplicity of illustration and explanation.
The successive-approximation-type AD converter of FIG. 1 includes capacitors C1 through C7, switches SW1 and SW2, NMOS transistors NM1 through NM9, and PMOS transistors PM1 through PM3. Vref is a reference potential, and Vin is an input analog potential that is applied to an analog input terminal. SPL is a control signal for controlling sampling operation, and CNTL is a control signal for controlling electric currents. OUT is an output of the successive-approximation-type AD converter. Furthermore, FIG. 1 shows an output node DACOUT of a capacitor DAC, internal nodes 30 through 34 of the successive-approximation-type AD converter, and a ground terminal GND.
FIG. 2 is a drawing for explaining the operation of the successive-approximation-type AD converter of FIG. 1.
As shown in FIG. 2, prior to the start of AD conversion, the current control signal CNTL is HIGH, and the sampling control signal SPL is LOW. When the current control signal CNTL is HIGH, the NMOS transistors NM7 through NM9 are conductive, so that the output node DACOUT of the capacitor DAC and the internal nodes 32 through 34 are kept at LOW. As a result, the NMOS transistors NM4 through NM6 are in a non-conductive state.
When AD conversion starts, the sampling control signal SPL is changed to HIGH and the current control signal CNTL is turned to LOW in order to sample an analog signal. With the current control signal CNTL being LOW, the NMOS transistors NM7 through NM9 become non-conductive. With the sampling control signal SPL being HIGH, further, the NMOS transistors NM1 through NM3 become conductive.
As NM1 turns on, the potential of the node DACOUT and the potential of the node 31 become equal. The PMOS transistor PM1 and the NMOS transistor NM4 together constitute an inverter at the first stage of the comparator. As an input and an output thereof are short-circuited as described above, the potential of the node DACOUT and the potential of the node 31 are set to a logical threshold (VTL) of the first stage of the comparator.
By the same token, as NM2 turns on, the input-and-output nodes 32 and 33 of the second stage (i.e., the PMOS transistor PM2 and the NMOS transistor NM5) of the comparator are set to a logical threshold VTL. Moreover, as NM3 turns on, the input-and-output nodes 34 and OUT of the third stage (i.e., the PMOS transistor PM3 and the NMOS transistor NM6) of the comparator are set to a logical threshold VTL. At this time, the voltage VTL is applied to the gates of the PMOS transistors PM1 through PM3 and the NMOS transistors NM4 through NM6, so that steady-state currents run through these transistors.
With the potential of the node DACOUT maintained at the logical threshold VTL, the sampling capacitors C1 through C5 are connected to the analog input terminal through the switches SW1 and SW2, and are thus charged with the input potential Vin.
The sampling capacitors C1 through C5 and the switch SW1 constitute a 4-bit DAC. The sampling capacitors C1 and C2 have capacitance Cx. Then, the sampling capacitor C3 is configured to have capacitance 2Cx, the sampling capacitor C4 configured to have capacitance 4Cx, and the sampling capacitor C5 configured to have capacitance 8Cx. In order to maintain relative accuracy, the sampling capacitors C3, C4, and C5 may be constructed by connecting 2, 4, and 8 capacitors in parallel, respectively, where such capacitors have the unit capacitance Cx of the sampling capacitors C1 and C2.
After sampling is finished, comparison is performed so as to determine each bit of digital data successively from the most significant bit. When this is done, both the current control signal CNTL and the sampling control signal SPL are set to LOW.
Specifically, the switches SW1 and SW2 are controlled in such a manner as to couple one of the two end nodes of the sampling capacitors C1 through C5 to either the ground potential or the reference potential Vref. For example, the sampling capacitors C1 through C4 are coupled to the ground potential, and the sampling capacitor C5 is coupled to the reference potential Vref. As a result, the potential of the node DACOUT is set at Vref/2−Vin+VTL. This potential of the node DACOUT is input into the three-stage comparator, thereby determining the magnitude relation of the analog input potential Vin relative to the reference potential Vref. In this manner, the most significant bit is determined.
Similarly, a potential of Vref/4−Vin+VTL or 3Vref/4−Vin+VTL is generated by controlling the switches SW1 and SW2, thereby determining the second bit from the top of the digital data. In a similar manner, each bit is determined successively from higher bits to lower bits. For example, the sampling capacitor C1 and the sampling capacitors C3 through C5 are coupled to the ground potential, and the sampling capacitor C2 is coupled to the reference potential Vref. In this case, the potential of the node DACOUT is set to Vref/16Vin+VTL.
In this manner, coupling is changed in units of capacitance Cx that is equal to one sixteenth of the total capacitance 16Cx (C1 through C5), so that the potential of the node DACOUT is changed in the increments of Vref/16. This makes it possible to determine 4-bit digital data.